43 lines
823 B
Verilog
43 lines
823 B
Verilog
`timescale 1ns/10ps
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`default_nettype none
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module gray_counter #(
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parameter SIZE=4
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) (
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input wire i_clk,
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input wire i_rst_n,
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input wire i_inc,
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output wire [SIZE-1:0] o_count_gray,
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output wire [SIZE-1:0] o_count_binn
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);
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reg [SIZE-1:0] state_gray;
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reg [SIZE-1:0] state_binn;
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reg [SIZE-1:0] logic_gray;
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reg [SIZE-1:0] logic_binn;
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always @(posedge i_clk or negedge i_rst_n) begin
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if (!i_rst_n) begin
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state_gray <= 0;
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state_binn <= 0;
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end
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else begin
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state_gray <= logic_gray;
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state_binn <= logic_binn;
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end
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end
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always @* begin
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logic_binn = state_binn + i_inc;
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logic_gray = (logic_binn>>1) ^ logic_binn;
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end
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assign o_count_gray = state_gray;
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assign o_count_binn = state_binn;
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endmodule
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`default_nettype none
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