46 lines
778 B
Verilog
46 lines
778 B
Verilog
`timescale 1ns/10ps
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`default_nettype wire
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module graytestbench;
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localparam aw = 8;
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function [aw:0] binn_to_gray;
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input [aw:0] binn;
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begin :b2g
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binn_to_gray = binn ^ (binn >> 1);
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end
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endfunction
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function [aw:0] gray_to_binn;
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input [aw:0] gray;
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begin :g2b
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reg [aw:0] binn;
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integer i;
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for(i=0; i <= aw; i = i+1) begin
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binn[i] = ^(gray >> i);
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end
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gray_to_binn = binn;
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end
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endfunction
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initial begin :test_graycode
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integer ii;
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reg[aw:0] gray;
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reg[aw:0] binn;
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for(ii=0; ii < 10; ii=ii+1) begin
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gray = binn_to_gray(ii[aw:0]);
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binn = gray_to_binn(gray);
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$display("test_graycode: i:%x gray:%x:%b binn:%x", ii[aw:0], gray, gray, binn);
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end
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$stop;
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end
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endmodule
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`default_nettype none
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