34 lines
659 B
Verilog
34 lines
659 B
Verilog
module Half_Adder( input a, b, output s, c );
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assign s = a ^ b;
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assign c = a & b;
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endmodule
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module Full_Adder( input a, b, c_in, output s, c_out );
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wire s_ha1, c_ha1, c_ha2;
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Half_Adder ha1( .a(c_in), .b(a), .s(s_ha1), .c(c_ha1) );
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Half_Adder ha2( .a(s_ha1), .b(b), .s(s), .c(c_ha2) );
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assign c_out = c_ha1 | c_ha2;
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endmodule
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module Multibit_Adder(a,b,s);
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parameter N = 8;
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input [N-1:0] a;
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input [N-1:0] b;
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output [N:0] s;
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wire [N:0] c;
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assign c[0] = 0;
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assign s[N] = c[N];
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generate
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genvar I;
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for (I=0; I<N; ++I) Full_Adder add( .a(a[I]), .b(b[I]), .s(s[I]), .c_in(c[I]), .c_out(c[I+1]) );
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endgenerate
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endmodule
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