21 lines
561 B
Verilog
21 lines
561 B
Verilog
program main;
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initial begin
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bit [52:0] a,b,c;
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a = 53'h123476547890fe;
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b = 53'h06453bdef23ca6;
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c = a & b; $display("%h & %h = %h", a,b,c);
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c = a | b; $display("%h | %h = %h", a,b,c);
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c = a ^ b; $display("%h ^ %h = %h", a,b,c);
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c = ~ a; $display("~%h = %h", a, c);
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c = a << 5; $display("%h << 5 = %h", a, c);
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c = a >> 5; $display("%h >> 5 = %h", a, c);
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c = { a[53-23:0], a[52-:23] }; $display("%h rotate-left 23 = %h", a, c);
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c = { a[1:0], a[52:2] }; $display("%h rotate-right 2 = %h", a, c);
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end
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endprogram
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