18 lines
395 B
VHDL
18 lines
395 B
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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entity g2b is
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port( gray : in std_logic_vector (4 downto 0);
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bin : buffer std_logic_vector (4 downto 0)
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);
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end g2b ;
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architecture rtl of g2b is
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constant N : integer := bin'high;
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begin
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bin(N) <= gray(N);
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gen_xor: for i in N-1 downto 0 generate
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bin(i) <= gray(i) xor bin(i+1);
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end generate;
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end architecture rtl;
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