15 lines
335 B
VHDL
15 lines
335 B
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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entity b2g is
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port( bin : in std_logic_vector (4 downto 0);
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gray : out std_logic_vector (4 downto 0)
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);
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end b2g ;
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architecture rtl of b2g is
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constant N : integer := bin'high;
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begin
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gray <= bin(n) & ( bin(N-1 downto 0) xor bin(N downto 1));
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end architecture rtl;
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