43 lines
1.5 KiB
Prolog
43 lines
1.5 KiB
Prolog
% binary 4 bit adder chip simulation
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b_not(in(hi), out(lo)) :- !. % not(1) = 0
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b_not(in(lo), out(hi)). % not(0) = 1
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b_and(in(hi,hi), out(hi)) :- !. % and(1,1) = 1
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b_and(in(_,_), out(lo)). % and(anything else) = 0
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b_or(in(hi,_), out(hi)) :- !. % or(1,any) = 1
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b_or(in(_,hi), out(hi)) :- !. % or(any,1) = 1
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b_or(in(_,_), out(lo)). % or(anything else) = 0
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b_xor(in(A,B), out(O)) :-
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b_not(in(A), out(NotA)), b_not(in(B), out(NotB)),
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b_and(in(A,NotB), out(P)), b_and(in(NotA,B), out(Q)),
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b_or(in(P,Q), out(O)).
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b_half_adder(in(A,B), s(S), c(C)) :-
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b_xor(in(A,B),out(S)), b_and(in(A,B),out(C)).
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b_full_adder(in(A,B,Ci), s(S), c(C1)) :-
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b_half_adder(in(Ci, A), s(S0), c(C0)),
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b_half_adder(in(S0, B), s(S), c(C)),
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b_or(in(C0,C), out(C1)).
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b_4_bit_adder(in(A0,A1,A2,A3), in(B0,B1,B2,B3), out(S0,S1,S2,S3), c(V)) :-
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b_full_adder(in(A0,B0,lo), s(S0), c(C0)),
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b_full_adder(in(A1,B1,C0), s(S1), c(C1)),
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b_full_adder(in(A2,B2,C1), s(S2), c(C2)),
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b_full_adder(in(A3,B3,C2), s(S3), c(V)).
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test_add(A,B,T) :-
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b_4_bit_adder(A, B, R, C),
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writef('%w + %w is %w %w \t(%w)\n', [A,B,R,C,T]).
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go :-
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test_add(in(hi,lo,lo,lo), in(hi,lo,lo,lo), '1 + 1 = 2'),
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test_add(in(lo,hi,lo,lo), in(lo,hi,lo,lo), '2 + 2 = 4'),
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test_add(in(hi,lo,hi,lo), in(hi,lo,lo,hi), '5 + 9 = 14'),
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test_add(in(hi,hi,lo,hi), in(hi,lo,lo,hi), '11 + 9 = 20'),
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test_add(in(lo,lo,lo,hi), in(lo,lo,lo,hi), '8 + 8 = 16'),
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test_add(in(hi,hi,hi,hi), in(hi,lo,lo,lo), '15 + 1 = 16').
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