75 lines
2.3 KiB
VHDL
75 lines
2.3 KiB
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY Factorial IS
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GENERIC (
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Nbin : INTEGER := 3 ; -- number of bit to input number
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Nbou : INTEGER := 13) ; -- number of bit to output factorial
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PORT (
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clk : IN STD_LOGIC ; -- clock of circuit
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sr : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- set and reset
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N : IN STD_LOGIC_VECTOR(Nbin-1 DOWNTO 0) ; -- max number
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Fn : OUT STD_LOGIC_VECTOR(Nbou-1 DOWNTO 0)); -- factorial of "n"
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END Factorial ;
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ARCHITECTURE Behavior OF Factorial IS
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---------------------- Program Multiplication --------------------------------
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FUNCTION Mult ( CONSTANT MFa : IN UNSIGNED ;
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CONSTANT MI : IN UNSIGNED ) RETURN UNSIGNED IS
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VARIABLE Z : UNSIGNED(MFa'RANGE) ;
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VARIABLE U : UNSIGNED(MI'RANGE) ;
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BEGIN
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Z := TO_UNSIGNED(0, MFa'LENGTH) ; -- to obtain the multiplication
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U := MI ; -- regressive counter
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LOOP
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Z := Z + MFa ; -- make multiplication
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U := U - 1 ;
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EXIT WHEN U = 0 ;
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END LOOP ;
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RETURN Z ;
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END Mult ;
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-------------------Program Factorial ---------------------------------------
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FUNCTION Fact (CONSTANT Nx : IN NATURAL ) RETURN UNSIGNED IS
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VARIABLE C : NATURAL RANGE 0 TO 2**Nbin-1 ;
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VARIABLE I : UNSIGNED(Nbin-1 DOWNTO 0) ;
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VARIABLE Fa : UNSIGNED(Nbou-1 DOWNTO 0) ;
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BEGIN
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C := 0 ; -- counter
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I := TO_UNSIGNED(1, Nbin) ;
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Fa := TO_UNSIGNED(1, Nbou) ;
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LOOP
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EXIT WHEN C = Nx ; -- end loop
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C := C + 1 ; -- progressive couter
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Fa := Mult (Fa , I ); -- call function to make a multiplication
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I := I + 1 ; --
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END LOOP ;
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RETURN Fa ;
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END Fact ;
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--------------------- Program TO Call Factorial Function ------------------------------------------------------
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TYPE Table IS ARRAY (0 TO 2**Nbin-1) OF UNSIGNED(Nbou-1 DOWNTO 0) ;
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FUNCTION Call_Fact RETURN Table IS
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VARIABLE Fc : Table ;
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BEGIN
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FOR c IN 0 TO 2**Nbin-1 LOOP
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Fc(c) := Fact(c) ;
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END LOOP ;
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RETURN Fc ;
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END FUNCTION Call_Fact;
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CONSTANT Result : Table := Call_Fact ;
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------------------------------------------------------------------------------------------------------------
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SIGNAL Nin : STD_LOGIC_VECTOR(N'RANGE) ;
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BEGIN -- start of architecture
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Nin <= N WHEN RISING_EDGE(clk) AND sr = "10" ELSE
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(OTHERS => '0') WHEN RISING_EDGE(clk) AND sr = "01" ELSE
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UNAFFECTED;
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Fn <= STD_LOGIC_VECTOR(Result(TO_INTEGER(UNSIGNED(Nin)))) WHEN RISING_EDGE(clk) ;
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END Behavior ;
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