INTCOMP  PROLOG
*                            Reg1=Addr(Addr(argA),Addr(argB))
         L     2,0(1)        Reg2=Addr(argA)
         L     3,4(1)        Reg3=Addr(argB)
         L     4,0(2)        Reg4=argA
         L     5,0(3)        Reg5=argA
         ST    4,A           Store R4 in A
         ST    5,B           Store R5 in B
*                            if (A < B)
         L     0,A           load R0
         C     0,B           compare
         BL    LOWER         branch if lower
*                            if (A = B)
         L     0,A           load R0
         C     0,B           compare
         BE    EQUAL         branch if equal
*                            if (A < B)
         L     0,A           load R0
         C     0,B           compare
         BH    GREATER       branch if higher
*                            other case ?
         B     RETURN
LOWER    WTO   'A<B'
         B     RETURN
EQUAL    WTO   'A=B'
         B     RETURN
GREATER  WTO   'A>B'
         B     RETURN
*
RETURN   EPILOG
A        DS    F             31-bit signed integer
B        DS    F             31-bit signed integer
         END